The present invention generally relates to a digital filter processor, and more particularly to a spacial filter having a finite impulse response filter.
Conventionally, spacial filter image processing is employed for smoothing, edge extraction, edge emphasizing and the like in a digital copying machine, facsimile machine, scanner and so on. In spacial filter image processing with respect to pixels arranged in n rows and n columns, a window of image is set which consists of 5.times.5 pixels having as the center a pixel A which is one of the 5 .times.5 pixels. Then, a corresponding filter factor is multiplied by each of the 5.times.5 image data of the window. Finally, the sum total of the multiplied image data is calculated. The sum total is data obtained by subjecting the pixel A to the spacial filter image process. Image data relating to each pixel is 6-bit image data capable of representing 64 tone levels.
For example, when an image matrix X which consists of 5.times.5 pixels xij is represented by formula (1), ##EQU1## and when a filter factor matrix W consisting of 5.times.5 filter factors Wij is represented by formula (2), ##EQU2## image data FW obtained after spacial filter image processing is represented as follows: ##EQU3##
FIG.1 is a block diagram of a spacial filter image processing device which implements spacial filter image processing with a 5.times.5 filter factor matrix W with respect to a 5.times.5 image matrix X. Referring to FIG.1, the spacial filter image processing device includes processing circuits 51 through 55, which perform an image processing for image data amounting to one line. Image data X11, X12, X13, X14 and X15 relating to pixels are supplied to multipliers M11, M12, M13, M14 and M15 of a processing circuit 51 in this order in accordance with the period of a predetermined clock signal. The multipliers M11, M12, M13, M14 and M15 have multiplication factors W11, W12, W13, W14 and W15, respectively. The multiplication result of the multiplier M11 is supplied to a register D11. The multiplication results supplied from the multipliers M12, M13, M14 and M15 are supplied to first input terminals of two-input adders A51, A52, A53 and A54, respectively. At this time, the register D51 temporarily stores the supplied data in accordance with the clock period, and supplies the stored data to the second input terminal of the adder A51. The adders A51 through A54 add the data at the first input terminals thereof and the data at the second input terminals, and supply the registers D52 through D55 with the addition results, respectively. In response to this operation, the registers D52 through D55 temporarily store the supplied data therein, and then supply the same with the adders A52, A53, A54, A55 and an adder ADD, respectively. The register D55 temporarily stores the supplied data with the clock period, and then outputs, as an output signal of the processing circuit 51, the stored data to a first input terminal of the adder ADD.
Each of the processing circuits 52 through 55 has the same structure as the processing circuit 51 except that they have corresponding multiplication factors. The processing circuits 52 through 55 subject image data X21 through X25, X31 through X35, X41 through X45, and X51 through X55 to an image filter process in the same way as the processing circuit 51. The operation results supplied from the processing circuits 52 through 55 are fed to the second through fifth input terminals of the adder ADD. The adder ADD adds all the data supplied through the first through fifth input terminals thereof, and outputs the image data FW which is the addition result.
For example, when a filter factor matrix Ws of a symmetrical image filtering process for an image is represented by the following formula, ##EQU4## an resultant image FWs of the spacial filter image process is represented as follows: ##EQU5##
However, in the above-mentioned conventional digital filter processors, 5 registers such as registers D51 through D55 are cascaded between the input and output terminals of the processing circuits 51 through 55. For this reason, it takes five times the aforementioned clock period to obtain the resultant of the spacial filter image process. Such a time is considerably long, and therefore it is necessary to reduce the processing time.